Share Email Print

Proceedings Paper

32-nm SOC printing with double patterning, regular design, and 1.2 NA immersion scanner
Author(s): Yorick Trouiller; Vincent Farys; Amandine Borjon; Jérôme Belledent; Christophe Couderc; Frank Sundermann; Jean-Christophe Urbani; Yves Rody; Christian Gardin; Jonathan Planchot; Will Conley; Pierre-Jerome Goirand; Scott Warrick; Frédéric Robert; Gurwan Kerrien; Florent Vautrin; Bill Wilkinson; Mazen Saied; Emic Yesilada; Patrick Montgomery; Laurent Le Cam; Catherine Martinelli
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

Resolution Enhancement Techniques (RET) are inherently design dependent technologies. To be successful the RET strategy needs to be adapted to the type of circuit desired. For SOC (system on chip), the three main patterning constraints come from: -Static RAM with very aggressive design rules specially at active, poly and contact -transistor variability control at the chip level -random layouts The development of regular layouts, within the framework of DFM, enables the use of more aggressive RET, pushing the required k1 factor further than allowed with existing RET techniques and the current wavelength and NA limitations. Besides that, it is shown that the primary appeal of regular design usage comes from the significant decrease in transistor variability. In 45nm technology a more than 80% variability reduction for the width and the length of the transistor at best conditions, and more than 50% variability reduction though the process window has been demonstrated. In addition, line-end control in the SRAM bitcell becomes a key challenge for the 32nm node. Taking all these constraints into account, we present the existing best patterning strategy for active and poly level of 32nm : -dipole with polarization and regular layout for active level -dipole with polarization, regular layout and double patterning to cut the line-end for poly level. These choices have been made based on the printing performances of a 0.17&mgr;m2 SRAM bitcell and a 32nm flip-flop with NA 1.2 immersion scanner.

Paper Details

Date Published: 27 March 2007
PDF: 12 pages
Proc. SPIE 6520, Optical Microlithography XX, 65201D (27 March 2007); doi: 10.1117/12.714116
Show Author Affiliations
Yorick Trouiller, LETI-CEA (France)
Vincent Farys, STMicroelectronics (France)
Amandine Borjon, Philips Semiconductors (France)
Jérôme Belledent, Philips Semiconductors (France)
Christophe Couderc, Philips Semiconductors (France)
Frank Sundermann, STMicroelectronics (France)
Jean-Christophe Urbani, STMicroelectronics (France)
Yves Rody, Philips Semiconductors (France)
Christian Gardin, Freescale Semiconductor (France)
Jonathan Planchot, STMicroelectronics (France)
Will Conley, Freescale Semiconductor (France)
Pierre-Jerome Goirand, STMicroelectronics (France)
Scott Warrick, Freescale Semiconductor (France)
Frédéric Robert, STMicroelectronics (France)
Gurwan Kerrien, STMicroelectronics (France)
Florent Vautrin, STMicroelectronics (France)
Bill Wilkinson, Freescale Semiconductor (France)
Mazen Saied, Freescale Semiconductor (France)
Emic Yesilada, Freescale Semiconductor (France)
Patrick Montgomery, Freescale Semiconductor (France)
Laurent Le Cam, Philips Semiconductors (France)
Catherine Martinelli, STMicroelectronics (France)

Published in SPIE Proceedings Vol. 6520:
Optical Microlithography XX
Donis G. Flagello, Editor(s)

© SPIE. Terms of Use
Back to Top