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Proceedings Paper

A systematic approach for capturing interconnects hot spots
Author(s): Mohamed Al-Imam; H. Y. Liao; Jochen Schacht; Te Hung Wu; Chia Wei Huang; Shen Yuan Huang; Pei Ru Tsai; Chuen Huei Yang
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Paper Abstract

Overlay variations between different layers in Integrated Circuits fabrication can result in poor circuit performance, even worst it can cause circuit mal function and consequently affect process yield. Coupled with other lithographic process variations this effect can be highly magnified. This leads to the fact that searching for interconnects hot spots should include overlay variations into account. The accuracy of inclusion of the overlay variation effect comes at the expense of a more complex simulation setup. Many issues should be taken into consideration including runtime, process combinations to be considered and the feasibility of providing a hint function for correction. In this paper we present a systematic approach for classification of interconnects durability through the lithographic process, taking into account focus, dose and overlay variations, the approach also provides information about the cause for the low durability that can be useful for building a more robust design. This classification can be accessible at the layout design level. With this information in hand, designers can test the layout while building up their circuit. Modifications to the layout for higher interconnects durability can be easily made. These modifications would be extremely expensive if they had to be made after design house tape out. We verify this method by showing real wafer failures, due to bad interconnect design, against interconnects' durability classifications from our method.

Paper Details

Date Published: 21 March 2007
PDF: 7 pages
Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65211C (21 March 2007); doi: 10.1117/12.713521
Show Author Affiliations
Mohamed Al-Imam, Mentor Graphics Corp. (United States)
H. Y. Liao, Mentor Graphics Corp. (United States)
Jochen Schacht, Mentor Graphics Corp. (United States)
Te Hung Wu, United Microelectronics Corp. (Taiwan)
Chia Wei Huang, United Microelectronics Corp. (Taiwan)
Shen Yuan Huang, United Microelectronics Corp. (Taiwan)
Pei Ru Tsai, United Microelectronics Corp. (Taiwan)
Chuen Huei Yang, United Microelectronics Corp. (Taiwan)


Published in SPIE Proceedings Vol. 6521:
Design for Manufacturability through Design-Process Integration
Alfred K.K. Wong; Vivek K. Singh, Editor(s)

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