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Proceedings Paper

Ensuring production-worthy OPC recipes using large test structure arrays
Author(s): Christopher Cork; Rainer Zimmermann; Xin Mei; Alexander Shahin
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Paper Abstract

The continual shrinking of design rules as the industry follows Moore's Law and the associated need for low k1 processes, have resulted in more layout configurations becoming difficult to print within the required tolerances. OPC recipes have needed to become more complex as tolerances decreased and acceptable corrections harder to find with simple algorithms. With this complexity comes the possibility of coding errors and ensuring the solutions are truly general. OPC Verification tools can check the quality of a correction based on pre-determined specifications for CD variation, line-end pullback and Edge Placement Error and then highlight layout configuration where violations are found. The problem facing a Mask Tape-Out group is that they usually have little control over the Design Styles coming in. Different approaches to eliminating problematic layouts have included highly restrictive Design Rules [1], whereby certain pitches or orientations are disallowed. Now these design rules are either becoming too complex or they overly restrict the designer from benefiting from the reduced pitch of the new node. The tight link between Design and Mask Tape-Out found in Integrated Device Manufacturers [2] (IDMs) i.e. companies that control both design and manufacturing can do much to dictate manufacturing friendly layout styles, and push ownership of problem resolution back to design groups. In fact this has been perceived as such an issue that a new class of products for designers that perform Lithographic Compliance Check on design layout is an emerging technology [3]. In contrast to IDMs, Semiconductor Foundries are presented with a much larger variety of design styles and a set of Fabless customers who generally are less knowledgeable in terms of understanding the impact of their layout on manufacturability and how to correct issues. The robustness requirements of a foundry's OPC correction recipe, therefore needs to be greater than that for an IDM's tape-out group. An OPC correction recipe which gives acceptable verification results, based solely on one customer GDS is clearly not sufficient to guarantee that all future tape-outs from multiple customers will be similarly clean. Ad hoc changes made in reaction to problems seen at verification are risky, while they may solve one particular layout issue on one product there is no guarantee that the problem may simply shift to another configuration on a yet to be manufactured part. The need to re-qualify a recipe over multiple products at each recipe change can easily results in excessive computational requirements. A single layer at an advanced node typically needs overnight runs on a large processor farm. Much of this layout, however, is extremely repetitive, made from a few standard cells placed tens of thousands of times. An alternative and more efficient approach, suggested by this paper as a screening methodology, is to encapsulate the problematic structures into a programmable test structure array. The dimensions of these test structures are parameterized in software such that they can be generated with these dimensions varied over the space of the design rules and conceivable design styles. By verifying the new recipe over these test structures one could more quickly gain confidence that this recipe would be robust over multiple tape-outs. This paper gives some examples of the implementation of this methodology.

Paper Details

Date Published: 21 March 2007
PDF: 9 pages
Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65211D (21 March 2007); doi: 10.1117/12.713411
Show Author Affiliations
Christopher Cork, Synopsys SARL (France)
Rainer Zimmermann, Synopsys GmbH (Germany)
Xin Mei, Synopsis (Singapore)
Alexander Shahin, Synopsis Israel, Ltd. (Israel)


Published in SPIE Proceedings Vol. 6521:
Design for Manufacturability through Design-Process Integration
Alfred K.K. Wong; Vivek K. Singh, Editor(s)

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