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Proceedings Paper

Feedback flow to improve model-based OPC calibration test patterns
Author(s): Walid A. Tawfic; Mohamed Al-Imam; Karim Madkour; Rami Fathy; Ir Kusnadi; George E. Bailey
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Paper Abstract

Process models are responsible for the prediction of the latent image in the resist in a lithographic process. In order for the process model to calculate the latent image, information about the aerial image at each layout fragment is evaluated first and then some aerial image characteristics are extracted. These parameters are passed to the process models to calculate wafer latent image. The process model will return a threshold value that indicates the position of the latent image inside the resist, the accuracy of this value will depend on the calibration data that were used to build the process model in the first place. The calibration structures used in building the models are usually gathered in a single layout file called the test pattern. Real raw data from the lithographic process are measured and attached to its corresponding structure in the test pattern, this data is then applied to the calibration flow of the models. In this paper we present an approach to automatically detect patterns that are found in real designs and have considerable aerial image parameters differences with the nearest test pattern structure, and repair the test patterns to include these structures. This detect-and-repair approach will guarantee accurate prediction of different layout fragments and therefore correct OPC behavior.

Paper Details

Date Published: 28 March 2007
PDF: 9 pages
Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65211J (28 March 2007); doi: 10.1117/12.712843
Show Author Affiliations
Walid A. Tawfic, Mentor Graphics Corp. (Egypt)
Mohamed Al-Imam, Mentor Graphics Corp. (Egypt)
Karim Madkour, Mentor Graphics Corp. (Egypt)
Rami Fathy, Mentor Graphics Corp. (Egypt)
Ir Kusnadi, Mentor Graphics Corp. (United States)
George E. Bailey, Mentor Graphics Corp. (United States)


Published in SPIE Proceedings Vol. 6521:
Design for Manufacturability through Design-Process Integration
Alfred K.K. Wong; Vivek K. Singh, Editor(s)

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