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Proceedings Paper

Process window optimization of CPL mask for beyond 45-nm lithography
Author(s): Soon Yoeng Tan; Qunying Lin; Cho Jui Tay; Chenggen Quan
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Paper Abstract

Chromeless Phase Lithography (CPL) has been used in sub-wavelength lithography resolution enhancement techniques (RET). As the device line width gets smaller toward 45nm technology and beyond, CPL process window optimization plays an important role to extend the limit of current optical lithography. In this study, 4 major areas of process window optimization are performed. Firstly, CPL data handling optimization and three-zone layout splitting are studied. Mask data is split into pure phase, zebra and pure chrome type based on the feature size. At the resolution limit, pure phase mask data type is used because the MEEF is low. Zebra mask data type will be used for feature size that is bigger than 75nm, while pure chrome feature is applied for feature sizes that are bigger than 180nm. Secondly, OAI and customize illumination optimization are studied. The 2D overlap region of the diffraction order within the entrance pupil is analyzed. The investigation shows that process window can be improved through background noise reduction and illumination optimization. Thirdly, polarization impact on high NA application is studied. Simulation results have shown DoF can be improved through the effect of polarization. Lastly, CPL mask quartz depth optimization and the effects of phase variation are studied. The investigation shows 180 degrees phase is not optimized for 193nm lithography. The effective phase for 193nm CPL is at 205 deg. With the above process window optimization, CPL demonstrates reasonable good process window on wafer printing. DoF with more than 0.3um on 65nm line with 160nm pitch has been achieved with using CPL under 0.85NA.

Paper Details

Date Published: 26 March 2007
PDF: 12 pages
Proc. SPIE 6520, Optical Microlithography XX, 652029 (26 March 2007); doi: 10.1117/12.712456
Show Author Affiliations
Soon Yoeng Tan, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Qunying Lin, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Cho Jui Tay, National Univ. of Singapore (Singapore)
Chenggen Quan, National Univ. of Singapore (Singapore)

Published in SPIE Proceedings Vol. 6520:
Optical Microlithography XX
Donis G. Flagello, Editor(s)

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