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Proceedings Paper

Prediction of interconnect delay variations using pattern matching
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Paper Abstract

An exploratory Process Variation Net Scanning (PVNS) approach to estimate interconnect delay variations is presented. It is shown that the geometrical response of lithographic nonidealities can be quickly predicted to first order with Pattern Matching. This concept can be extended to other process nonidealities by developing Maximum Lateral Impact Functions to capture the effects of variations in conductor sidewall angle and thickness from etch and CMP processes. The geometrical response for each variation can then be used to model the effective change in resistance and capacitance and perturb the corresponding values in the extracted netlist. The impact of PVNS is demonstrated using a 90nm digital design, and the runtime analysis indicates that this approach may potentially be twice as fast as traditional extraction. This allows for fast electrical analysis of independent process variations on different interconnect layers instead of traditional best and worst case corner analyses.

Paper Details

Date Published: 21 March 2007
PDF: 6 pages
Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65210I (21 March 2007); doi: 10.1117/12.712257
Show Author Affiliations
Eric Y. Chin, Univ. of California, Berkeley (United States)
Juliet A. Holwill, Univ. of California, Berkeley (United States)
Andrew R. Neureuther, Univ. of California, Berkeley (United States)

Published in SPIE Proceedings Vol. 6521:
Design for Manufacturability through Design-Process Integration
Alfred K.K. Wong; Vivek K. Singh, Editor(s)

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