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Proceedings Paper

Statistical analysis of gate CD variation for yield optimization
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Paper Abstract

A new method for analysis of variation and yield across the whole chip is presented. This method takes into account the stochastic distribution of the input process parameters such as focus and exposure, and performs simulations of the design at the extreme points of the process window. Using a robust model to extrapolate the points within the process window, a full distribution of CDs is produced for each gate, which then is analyzed to provide information about both the individual gate and the variation across the chip.

Paper Details

Date Published: 21 March 2007
PDF: 8 pages
Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65211P (21 March 2007); doi: 10.1117/12.712178
Show Author Affiliations
Juliet Holwill, Univ. of California, Berkeley (United States)
Jongwook Kye, Advanced Micro Devices (United States)
Yi Zou, Advanced Micro Devices (United States)


Published in SPIE Proceedings Vol. 6521:
Design for Manufacturability through Design-Process Integration
Alfred K.K. Wong; Vivek K. Singh, Editor(s)

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