Share Email Print
cover

Proceedings Paper

Highly accurate model-based verification using SEM image calibration method
Author(s): Byung-ug Cho; Dae-jin Park; Dong-suk Chang; Jae-seung Choi; Cheol-Kyun Kim; DongGyu Yim; Ju-Byung Kim
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

In the past when design rule is not tight, CD-based OPC modeling was acceptable. But shrinkage of design rule eventually led to small process window, which in part increased MEEF(Mask Error Enhancement Factor). Hence, data for OPC modeling have also become more complex and diverse in order to characterize the critical OPC models. The number of measurement points for OPC model evaluation has increased to several hundred points per layer, and metrology requests for realizing pattern shapes on the wafer are no longer simple one-dimensional measurements. Traditional CD-based OPC modeling is based on 1 dimensional parameter fitting and has limited information. Due to this reason, the accuracy of the model has intrinsic limitations. Recently, development of modeling methodology resulted in SEM image calibration. SEM image calibration use SEM image to calibrate large volume 2 dimensional information. SEM image calibration is based on real SEM image which has several thousands of CD information. It needs only SEM images instead of several hundred CD data, so data feedback is more easy. But this approach makes it difficult to achieve confidential level for predictability because SEM image is restricted to local region. And modeling accuracy is highly dependent on SEM image quality and local position. In this paper, we propose SEM image calibration method that feeds back SEM image calibrated model to model-based verification. By using this method, modeling accuracy is increased and better post OPC verification can be made. We will discuss the application result on sub-60nm device and the feasibility of this approach.

Paper Details

Date Published: 21 March 2007
PDF: 7 pages
Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65210R (21 March 2007); doi: 10.1117/12.712037
Show Author Affiliations
Byung-ug Cho, Hynix Semiconductor, Inc. (South Korea)
Dae-jin Park, Hynix Semiconductor, Inc. (South Korea)
Dong-suk Chang, Hynix Semiconductor, Inc. (South Korea)
Jae-seung Choi, Hynix Semiconductor, Inc. (South Korea)
Cheol-Kyun Kim, Hynix Semiconductor, Inc. (South Korea)
DongGyu Yim, Hynix Semiconductor, Inc. (South Korea)
Ju-Byung Kim, Brion Technology (United States)


Published in SPIE Proceedings Vol. 6521:
Design for Manufacturability through Design-Process Integration
Alfred K.K. Wong; Vivek K. Singh, Editor(s)

© SPIE. Terms of Use
Back to Top