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Proceedings Paper

Improvement of front-end process overlay in 60nm DRAM
Author(s): Young-Sun Hwang; Won-Kwang Ma; Eung-Kil Kang; Chang-Moon Lim; Seung-Chan Moon; Sang-Jin An; Kyu-Kab Rhe
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Paper Abstract

ArF immersion lithography and RETs (Resolution Enhancement Technology) are the most promising technology for sub 60nm patterning. As the device size shrinks, overlay accuracy has become more important due to small overlap margin between layers. Overlay performance of immersion process is affected by thermal effect due to water evaporation, so it shows worse performance than dry process and CD variation in DPT (Double Patterning Technology) process is affected by overlay performance. So improvement of overlay accuracy became hot issue in realization of future lithography technology, especially immersion process and double patterning process. Current status of lithography tool shows 10 ~ 12nm (3sigma) overlay control in front-end process, but this overlay performance is not sufficient for future technology. In this paper, we investigated the causes of overlay variation and tried to improve overlay accuracy in front-end process of 60nm DRAM device. Therefore, the results in this study can be implemented to new technology such as immersion and double patterning. First, overlay residual error factor is classified into two types, one is the equipment error factor and the other is process error factor. Equipment error can be divided into SCMV (Single Chuck Mean Variation) by stage accuracy variation, chuck to chuck mean and correction factor variation by using twin chuck etc. And process error can be divided into alignment signal variation by chuck defocus (stage particle by contamination), increase of overlay residual by material deposition, alignment key height variation by etch loading effect, overlay vernier attack by CMP (Chemical Mechanical Polishing) process etc. We analyzed causes of these overlay error factor and we applied new system and process to improve these overlay error factor. In conclusion, we were able to find where overlay error comes from and how to improve overlay accuracy in 60nm device, and we got good overlay performance using new alignment system and process optimization.

Paper Details

Date Published: 12 April 2007
PDF: 7 pages
Proc. SPIE 6518, Metrology, Inspection, and Process Control for Microlithography XXI, 65182Y (12 April 2007); doi: 10.1117/12.712025
Show Author Affiliations
Young-Sun Hwang, Hynix Semiconductor Industries Co., Ltd. (South Korea)
Won-Kwang Ma, Hynix Semiconductor Industries Co., Ltd. (South Korea)
Eung-Kil Kang, Hynix Semiconductor Industries Co., Ltd. (South Korea)
Chang-Moon Lim, Hynix Semiconductor Industries Co., Ltd. (South Korea)
Seung-Chan Moon, Hynix Semiconductor Industries Co., Ltd. (South Korea)
Sang-Jin An, ASML (South Korea)
Kyu-Kab Rhe, ASML (South Korea)


Published in SPIE Proceedings Vol. 6518:
Metrology, Inspection, and Process Control for Microlithography XXI
Chas N. Archie, Editor(s)

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