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Proceedings Paper

Improving the power-performance of multicore processors through optimization of lithography and thermal processing
Author(s): A. H. Gabor; T. Brunner; S. Bukofsky; S. Butt; F. Clougherty; S. Deshpande; T. Faure; O. Gluschenkov; K. Greene; J. Johnson; N. Le; P. Lindo; A. P. Mahorowala; H-J. Nam; D. Onsongo; D. Poindexter; J. Rankin; N. Rohrer; S. Stiffler; A. Thomas; H. Utomo
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Paper Abstract

It is generally assumed that achieving a narrow distribution of physical gate length (Lpoly) for the poly conductor layer helps improve power performance metrics of modern integrated circuits. However, in advanced 90 nm technologies, there are other drivers of chip performance. In this paper we show that a global optimization of all variables is necessary to achieve the optimum performance at the lowest leakage. We will also describe how systematic physical gate-length variation can improve core matching in multicore designs.

Paper Details

Date Published: 21 March 2007
PDF: 7 pages
Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65210K (21 March 2007); doi: 10.1117/12.711750
Show Author Affiliations
A. H. Gabor, IBM (United States)
T. Brunner, IBM (United States)
S. Bukofsky, IBM (United States)
S. Butt, IBM (United States)
F. Clougherty, IBM (United States)
S. Deshpande, IBM (United States)
T. Faure, IBM (United States)
O. Gluschenkov, IBM (United States)
K. Greene, IBM (United States)
J. Johnson, IBM (United States)
N. Le, IBM (United States)
P. Lindo, IBM (United States)
A. P. Mahorowala, IBM (United States)
H-J. Nam, IBM (United States)
D. Onsongo, IBM (United States)
D. Poindexter, IBM (United States)
J. Rankin, IBM (United States)
N. Rohrer, IBM (United States)
S. Stiffler, IBM (United States)
A. Thomas, IBM (United States)
H. Utomo, IBM (United States)


Published in SPIE Proceedings Vol. 6521:
Design for Manufacturability through Design-Process Integration
Alfred K.K. Wong; Vivek K. Singh, Editor(s)

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