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Proceedings Paper

Cost-performance tradeoff between design and manufacturing: DfM or MfD?
Author(s): A. Balasinski; J. Cetin; L. Karklin
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Paper Abstract

Design, CAD, and manufacturing are focused on optimizing translation methodology from electrical design to physical layout, and finally to mask data. The general goal is to improve integrated circuit (IC) functionality, reliability, manufacturability, testability, etc., using Design-for-X-ability (DfX) rules. Among those, the key role is played by DfM which is most directly related to the yield and therefore, the profit. A lot of pressure is being put on design to improve their understanding of all technology implementation issues, such that the mask pattern generated out of design layout would be "correct by construction" and comply with all of them. One can expect that such DfM-compliant layout should require significant effort to create, and its salient features would include: Manhattan geometries, and restricted grid for critical geometries, such as poly gates, large enclosures of the active area in the corners of implant layers, complete symmetry and proximity of the matched devices on all masking levels, minimal amount of jogs even for the complex features, neat alignment of source and drain contacts, line ends of gates and interconnects, doubled contacts and vias, etc. The question is if the cost of following all these practices at design time is not higher than that of other design improvement options. One alternative approach is to automatically adjust the "draft" layout using CAD post-processing such that all geometries would be optimized to conform to the DfM rules. Another approach to the DfM methodology is to improve the manufacturing capabilities such that the process tools would be able to achieve high yield for a layout which conforms only to some basic set of rules. This approach becomes even more relevant when the product line tries to address only selected DfM issues to improve die performance where it is most needed. We discussed the layout flow charts to determine the best approach, depending on the direct cost of the solution, the wafer volume, product time to market, and the risks involved.

Paper Details

Date Published: 21 March 2007
PDF: 7 pages
Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65210L (21 March 2007); doi: 10.1117/12.711709
Show Author Affiliations
A. Balasinski, Cypress Semiconductor (United States)
J. Cetin, Cypress Semiconductor (United States)
L. Karklin, Sagantec Corp. (United States)


Published in SPIE Proceedings Vol. 6521:
Design for Manufacturability through Design-Process Integration
Alfred K.K. Wong; Vivek K. Singh, Editor(s)

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