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Proceedings Paper

Benefit of ArF immersion lithography in 55 nm logic device manufacturing
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Paper Abstract

In this paper we demonstrate the many benefits of using immersion lithography that go beyond depth of focus (DOF) improvement by comparing several key features of dry and immersion lithography. Immersion lithography improves critical dimension uniformity (CDU) as well as avoiding the necessity for strong resolution enhancement techniques (RET) as compared with dry lithography. Thus it is possible to significantly reduce the burden of optical proximity correction (OPC) work with immersion lithography. With respect to imaging, we studied the sensitivity of the lithographic performances to aberrations and light source spectral bandwidth E95 fluctuations to highlight the benefits of immersion lithography. The significant improvements that have been seen in the last year in overlay accuracy, defect control and focus & leveling accuracy have been considered to be challenges to the realization of immersion lithography in mass production. Now these challenges have been met for the manufacturing requirements of 55 nm logic devices. The achievements of immersion lithography include overlay accuracy within 10 nm on resist-to-resist wafers and within 20 nm on production wafers, fewer than 10 defects per wafer, and errors of less than 40 nm in focus & leveling on full wafers. We have established a top-coat resist process. In conclusion, immersion lithography is the most promising manufacturing solution for 55 nm node logic devices, providing advantages in CDU control, and equivalent overlay performance and focus & leveling accuracy to dry ArF, without an increased level of defects. NEC Electronics has completed development and preproduction of the 55 nm logic device "UX7LS" using immersion lithography and has established the lithography technology for mass production of the UX7LS this year.

Paper Details

Date Published: 26 March 2007
PDF: 10 pages
Proc. SPIE 6520, Optical Microlithography XX, 652009 (26 March 2007); doi: 10.1117/12.711054
Show Author Affiliations
Takayuki Uchiyama, NEC Electronics Corp. (Japan)
Takao Tamura, NEC Electronics Corp. (Japan)
Kazuyuki Yoshimochi, NEC Electronics Corp. (Japan)
Paul Graupner, Carl Zeiss, Semiconductor Manufacturing Technology AG (Germany)
Hans Bakker, ASML (Netherlands)
Eelco van Setten, ASML (Netherlands)
Kenji Morisaki, ASML Japan (Japan)

Published in SPIE Proceedings Vol. 6520:
Optical Microlithography XX
Donis G. Flagello, Editor(s)

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