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Proceedings Paper

Advanced defect definition method using design data
Author(s): Kyuhong Lim; Dilip Patel; Kyoungmo Yang; Shunsuke Koshihara; Lorena Page; Andy Self; Maurilio Martinez
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Paper Abstract

As Moore's Law indicates, pattern feature sizes have become smaller and smaller, increasing the need for more critical metrology and inspection methodologies in integrated circuit fabrication. Critical methodologies are especially required in the inspection area where more critical defect definition methods are needed for the accurate evaluation of inspection tools. In traditional defect definition, we have to use only normal CD measurement results with manual measurement methods. This one dimensional definition method gives only defect size information which is not enough information to do accurate evaluation. In addition, there is a lot of measurement uncertainty such as human errors, measurement errors, and systematic errors which are included in the data of manual measurement methods. Because of these mentioned issues, evaluation results will differ from person to person and other environmental influences. In this paper, the defects will be defined not only with one dimensional measurement but also with two dimensional measurements using such functions as Gap measurement and EPE (Edge Placement Error) measurement in DesignGauge using Design Data. For example, misplacement defects in which a pattern is shifted on the wafer as shown in figure 1 below; traditional one dimension measurement methods can not detect this type of defect. However, with DesignGauge, misplacement defects can easily be detected if the Design Data is used as shown in figure 2. EPE measurement method, which is one of the advanced features of DesignGauge, will accurately define misplacement defects. As the trends of smaller feature sizes in integrated circuit fabrication continues, various defects should be controlled and measured with advanced defect definition methods using Design Data.

Paper Details

Date Published: 5 April 2007
PDF: 10 pages
Proc. SPIE 6518, Metrology, Inspection, and Process Control for Microlithography XXI, 65184A (5 April 2007); doi: 10.1117/12.711026
Show Author Affiliations
Kyuhong Lim, International SEMATECH Manufacturing Initiative (United States)
Dilip Patel, International SEMATECH Manufacturing Initiative (United States)
Kyoungmo Yang, Hitachi High-Technologies Corp. (Japan)
Shunsuke Koshihara, Hitachi High-Technologies Corp. (Japan)
Lorena Page, Hitachi High-Technologies America, Inc. (United States)
Andy Self, Hitachi High-Technologies America, Inc. (United States)
Maurilio Martinez, Hitachi High-Technologies America, Inc. (United States)

Published in SPIE Proceedings Vol. 6518:
Metrology, Inspection, and Process Control for Microlithography XXI
Chas N. Archie, Editor(s)

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