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Proceedings Paper

Modeling spatial gate length variation in the 0.2µm to 1.15mm separation range
Author(s): Paul Friedberg; Willy Cheung; George Cheng; Qian Ying Tang; Costas J. Spanos
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Paper Abstract

Circuit performance variability is significantly impacted by variations in gate length caused in microlithographic pattern transfer [1]. Previous studies [2] have shown through simulation that by completely reconciling sources of deterministic variation, long-range (millimeter separation scale) spatial correlation in the remaining variation is virtually zero. To complete the model for spatial variation and correlation in critical dimension (CD), a new set of electrical linewidth metrology (ELM) test structures were then designed to target the sub-mm regime [3]. In this work, we report measurement results from those micron-scale ELM test structures. The micron-scale (0.2μm to 1.15mm) variation can be decomposed into a very large chip-to-chip component, a small and systematic density-dependent component, and a small random component; spatial correlation in gate length for the micron-scale regime is negligible.

Paper Details

Date Published: 21 March 2007
PDF: 11 pages
Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 652119 (21 March 2007); doi: 10.1117/12.710668
Show Author Affiliations
Paul Friedberg, Univ. of California, Berkeley (United States)
Willy Cheung, Columbia Univ. (United States)
George Cheng, Univ. of California, Berkeley (United States)
Qian Ying Tang, Univ. of California, Berkeley (United States)
Costas J. Spanos, Univ. of California, Berkeley (United States)

Published in SPIE Proceedings Vol. 6521:
Design for Manufacturability through Design-Process Integration
Alfred K.K. Wong; Vivek K. Singh, Editor(s)

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