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Proceedings Paper

Characterization of line-edge roughness in Cu/low-k interconnect pattern
Author(s): Atsuko Yamaguchi; Daisuke Ryuzaki; Jiro Yamamoto; Hiroki Kawada; Takashi Iizumi
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Paper Abstract

To establish a method for measuring interconnect line-edge roughness (LER), low-k line patterns were observed and electric-field concentration was simulated based on the observation results. Wedges were observed on the edges, and the bottom and the top widths of the average wedge feature were 60 nm and 7 nm (or smaller), respectively. Simulation showed that the LER causes serious degradation of TDDB immunity at 100-nm-pitch Cu/low-k interconnects. The maximum electric-field intensity depends upon the conventional LER metric, 3Rq, but depends more strongly on the wedge angle, the curvature of the tip, and the minimum linewidth.

Paper Details

Date Published: 5 April 2007
PDF: 8 pages
Proc. SPIE 6518, Metrology, Inspection, and Process Control for Microlithography XXI, 65181P (5 April 2007); doi: 10.1117/12.710401
Show Author Affiliations
Atsuko Yamaguchi, Hitachi, Ltd. (Japan)
Daisuke Ryuzaki, Hitachi, Ltd. (Japan)
Jiro Yamamoto, Hitachi, Ltd. (Japan)
Hiroki Kawada, Hitachi High-Technologies Corp. (Japan)
Takashi Iizumi, Hitachi High-Technologies Corp. (Japan)

Published in SPIE Proceedings Vol. 6518:
Metrology, Inspection, and Process Control for Microlithography XXI
Chas N. Archie, Editor(s)

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