Share Email Print
cover

Proceedings Paper

Shared transistor architecture with diagonally connected pixels for a CMOS image sensor
Author(s): Yoshiharu Kudoh; Fumihiko Koga; Takashi Abe; Haruyuki Taniguchi; Maki Sato; Hiroaki Ishiwata; Susumu Ooki; Ryoji Suzuki; Hiroyuki Mori
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

We have developed a pixel unit for CMOS image sensors (CISs) that has a shared transistor architecture with diagonally connected pixels. This pixel unit is composed of four photodiodes and seven transistors. It has a pixel size of 2.5-&mgr;m square. The transistors were designed using 0.18-micron aluminum process technology. Shared diffusion for reading signal electrons occurs between the corners of two photodiodes. The advantages of this layout include a long amplifier gate length and a large photodiode area.

Paper Details

Date Published: 21 February 2007
PDF: 8 pages
Proc. SPIE 6501, Sensors, Cameras, and Systems for Scientific/Industrial Applications VIII, 65010G (21 February 2007); doi: 10.1117/12.704835
Show Author Affiliations
Yoshiharu Kudoh, Sony Corp. (Japan)
Fumihiko Koga, Sony Corp. (Japan)
Takashi Abe, Sony Corp. (Japan)
Haruyuki Taniguchi, Sony Corp. (Japan)
Maki Sato, Sony Corp. (Japan)
Hiroaki Ishiwata, Sony Corp. (Japan)
Susumu Ooki, Sony Corp. (Japan)
Ryoji Suzuki, Sony Corp. (Japan)
Hiroyuki Mori, Sony Corp. (Japan)


Published in SPIE Proceedings Vol. 6501:
Sensors, Cameras, and Systems for Scientific/Industrial Applications VIII
Morley M. Blouke, Editor(s)

© SPIE. Terms of Use
Back to Top