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Proceedings Paper

CMOS minimal array
Author(s): James Janesick; John Cheng; Jeanne Bishop; James T. Andrews; John Tower; Jeff Walker; Mark Grygon; Tom Elliot
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Paper Abstract

A high performance prototype CMOS imager is introduced. Test data is reviewed for different array formats that utilize 3T photo diode, 5T pinned photo diode and 6T photo gate CMOS pixel architectures. The imager allows several readout modes including progressive scan, snap and windowed operation. The new imager is built on different silicon substrates including very high resistivity epitaxial wafers for deep depletion operation. Data products contained in this paper focus on sensor's read noise, charge capacity, charge transfer efficiency, thermal dark current, RTS dark spikes, QE, pixel cross- talk and on-chip analog circuitry performance.

Paper Details

Date Published: 7 September 2006
PDF: 15 pages
Proc. SPIE 6295, Infrared Detectors and Focal Plane Arrays VIII, 62950O (7 September 2006); doi: 10.1117/12.693204
Show Author Affiliations
James Janesick, Sarnoff Corp. (United States)
John Cheng, Chronicle Technology Inc. (United States)
Jeanne Bishop, Chronicle Technology Inc. (United States)
James T. Andrews, Sarnoff Corp. (United States)
John Tower, Sarnoff Corp. (United States)
Jeff Walker, Sarnoff Corp. (United States)
Mark Grygon, Sarnoff Corp. (United States)
Tom Elliot, Jet Propulsion Lab. (United States)

Published in SPIE Proceedings Vol. 6295:
Infrared Detectors and Focal Plane Arrays VIII
Eustace L. Dereniak; Robert E. Sampson, Editor(s)

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