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Proceedings Paper

Process results using automatic pitch decomposition and double patterning technology (DPT) at k1eff <0.20
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Paper Abstract

In conventional IC processes, the smallest size of any features that can be created on a wafer is severely limited by the pitch of the processing system. Double patterning technology is a key enabler of printing mask features on wafers as a hybrid extension to optical approaches with new litho-aware design methods and tools, optical equipment, and process flows. The approach does not require restrictions on the design of the chip. This paper will discuss the method and full-chip decomposition tool used to determine locations to split the layout. It will demonstrate examples of over-constrained layouts and how these configurations are mitigated. It will also show the reticle enhancement techniques used to process the split layouts and the Lithographic Checking. A new type of "hotspot" is identified through simulation and tools to identify, repair and verify are shown. Lithography results are shown with effective k1<0.2 for logic and flash memory patterns.

Paper Details

Date Published: 20 October 2006
PDF: 11 pages
Proc. SPIE 6349, Photomask Technology 2006, 634910 (20 October 2006); doi: 10.1117/12.687747
Show Author Affiliations
Judy Huckabay, Cadence Design Systems, Inc. (United States)
Wolf Staud, Cadence Design Systems, Inc. (United States)
Robert Naber, Cadence Design Systems, Inc. (United States)
Anton van Oosten, ASML, Inc. (Netherlands)
Peter Nikolski, ASML, Inc. (United States)
Stephen Hsu, ASML, Inc. (United States)
R. J. Socha, ASML, Inc. (United States)
M. V. Dusa, ASML, Inc. (United States)
Donis Flagello, ASML, Inc. (United States)


Published in SPIE Proceedings Vol. 6349:
Photomask Technology 2006
Patrick M. Martin; Robert J. Naber, Editor(s)

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