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Proceedings Paper

A procedure and program to calculate shuttle mask advantage
Author(s): A. Balasinski; J. Cetin; A. Kahng; X. Xu
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Paper Abstract

A well-known recipe for reducing mask cost component in product development is to place non-redundant elements of layout databases related to multiple products on one reticle plate [1,2]. Such reticles are known as multi-product, multi-layer, or, in general, multi-IP masks. The composition of the mask set should minimize not only the layout placement cost, but also the cost of the manufacturing process, design flow setup, and product design and introduction to market. An important factor is the quality check which should be expeditious and enable thorough visual verification to avoid costly modifications once the data is transferred to the mask shop. In this work, in order to enable the layer placement and quality check procedure, we proposed an algorithm where mask layers are first lined up according to the price and field tone [3]. Then, depending on the product die size, expected fab throughput, and scribeline requirements, the subsequent product layers are placed on the masks with different grades. The actual reduction of this concept to practice allowed us to understand the tradeoffs between the automation of layer placement and setup related constraints. For example, the limited options of the numbers of layer per plate dictated by the die size and other design feedback, made us consider layer pairing based not only on the final price of the mask set, but also on the cost of mask design and fab-friendliness. We showed that it may be advantageous to introduce manual layer pairing to ensure that, e.g., all interconnect layers would be placed on the same plate, allowing for easy and simultaneous design fixes. Another enhancement was to allow some flexibility in mixing and matching of the layers such that non-critical ones requiring low mask grade would be placed in a less restrictive way, to reduce the count of orphan layers. In summary, we created a program to automatically propose and visualize shuttle mask architecture for design verification, with enhancements to due to the actual application of the code.

Paper Details

Date Published: 20 October 2006
PDF: 8 pages
Proc. SPIE 6349, Photomask Technology 2006, 63492B (20 October 2006); doi: 10.1117/12.686009
Show Author Affiliations
A. Balasinski, Cypress Semiconductor (United States)
J. Cetin, Cypress Semiconductor (United States)
A. Kahng, Univ. of California, San Diego (United States)
X. Xu, Univ. of California, San Diego (United States)


Published in SPIE Proceedings Vol. 6349:
Photomask Technology 2006
Patrick M. Martin; Robert J. Naber, Editor(s)

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