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Proceedings Paper

The study of chromeless phase lithography (CPL) for 45nm lithography
Author(s): Soon Yoeng Tan; Qunying Lin; Cho Jui Tay; Chenggen Quan
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Paper Abstract

Chromeless Phase Lithography (CPL) has been used to achieve high resolution by using phase edge interference in addition with high NA and off-axis illuminations such as annular and quasar for sub-wavelength lithography. There are two types of CPL. One is the totally chromeless pure phase type and the other is the zebra chrome pattern type for critical line dimensions. Both types of CPL masks require adding in chrome pads in some structures such as circuit line junction region to improve the resolution. Zebra type CPL mask making has reached the limitation due to small chrome peeling issue during mask cleaning and small space writing resolution issue for sub-45nm technology. In this paper, two types of CPL masks are studied. The investigation shows the differences on mask making and wafer performance. For mask making, process limitation studies such as writing, etching and cleaning will be evaluated. Data on mask CD (Critical Dimension) performance, registration, overlay, phase and transmission are collected and analyzed. For wafer performance, process window comparison, CD through pitch, MEEF (Mask Error Enhancement Factor) and linearity will be characterized for these two CPL mask types. Minimum resolution of less than 160nm pitch with reasonable good process window has been achieved with both mask types. Chromeless pure phase type has advantages on mask making while zebra type has the advantages on wafer performance. Furthermore, SRAF (Sub-Resolution Assist Feature) are added to improve wafer printing process windows. Detailed characterization work done on assist features are presented. Assist feature can improve process window by improving the contrast of isolated lines.

Paper Details

Date Published: 20 October 2006
PDF: 11 pages
Proc. SPIE 6349, Photomask Technology 2006, 63492O (20 October 2006); doi: 10.1117/12.685887
Show Author Affiliations
Soon Yoeng Tan, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Qunying Lin, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Cho Jui Tay, National Univ. of Singapore (Singapore)
Chenggen Quan, National Univ. of Singapore (Singapore)


Published in SPIE Proceedings Vol. 6349:
Photomask Technology 2006
Patrick M. Martin; Robert J. Naber, Editor(s)

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