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Proceedings Paper

Hardware implementation and characterization of a low density parity check (LDPC) decoder
Author(s): Ryan Shoup
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Paper Abstract

The hardware implementation of a low complexity Low Density Parity Check (LDPC) decoder is described. The design of the LDPC decoder optimized on minimizing the amount of hardware resources necessary for implementation. In addition to implementation details, design tradeoffs considered in the development of the LDPC decoder are discussed. The intended application of the LDPC decoder is a nonlinear satellite communications channel. The nonlinearities and communications signal perturbations include Additive White Gaussian Noise (AWGN), phase noise, phase imbalance, and a model satellite high power amplifier nonlinearity. The LDPC decoder performance is then characterized in the satellite channel.

Paper Details

Date Published: 1 September 2006
PDF: 8 pages
Proc. SPIE 6300, Satellite Data Compression, Communications, and Archiving II, 63000E (1 September 2006); doi: 10.1117/12.682607
Show Author Affiliations
Ryan Shoup, MIT/Lincoln Lab. (United States)


Published in SPIE Proceedings Vol. 6300:
Satellite Data Compression, Communications, and Archiving II
Roger W. Heymann; Charles C. Wang; Timothy J. Schmit, Editor(s)

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