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Proceedings Paper

Automated hot-spot fixing system applied for metal layers of 65 nm logic devices
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Paper Abstract

Hot spot clearance using process simulation is indispensable under low-k1 lithography process for logic devices of 65 nm and below. Hot spots such as pinching, bridging, line-end shortening will occur, mainly depending on local pattern context. Appropriate calibration of design rule (DR), mask data preparation (MDP), resolution enhancement technique (RET) and optical proximity effect correction (OPC) will reduce potential hot spots. However, pattern layout variety is so enormous that, even with the most careful calibration of every process, an unexpected potential hot spot is occasionally left in the design layout. Manual modification of design at hot spot will be effective, but it takes too much time to determine how to modify layout to be consistent with DR, MDP/OPC rule, and the process often needs to be iterative. Therefore, there is a need for an automated hot spot fixing system is capable of fixing design layout so as to avoid fatal hot spot occurrence, with sufficient process margin and short turn around time (TAT). We developed an automated hot-spot fixing system, Hot Spot Fixer (HSF). The basic system flow in the developed system is as follows; Design data is processed with the conventional mask data preparation process. Then, process simulation is performed to extract hot spots. The hot spots are categorized by lithography error mode, critical level, and surrounding context. An intelligent hot-spot modification instructor, taking the surrounding situation into consideration, generates modification guide for the every hot spot. Design data is automatically modified according to the instruction at every hot spot, complying with the design rule. If necessary, several modification candidates are indicated and the user can choose the most adequate one from them. The design modification process is verified from every aspect, using Design Rule Checker (DRC) and process simulation. The modified design data, with reduced potential hot spot compared with pre-modification design, is processed under the conventional mask data preparation process again, and then makes mask data, which will reduce the number of potential hot spot. We applied the HSF system to metal layer of logic devices of 65 nm and then the hot spots are almost diminished throughout a full chip within twelve hours. Thus HSF feasibility has been proved for metal layers in 65 nm node and below with full chip data volume.

Paper Details

Date Published: 20 May 2006
PDF: 11 pages
Proc. SPIE 6283, Photomask and Next-Generation Lithography Mask Technology XIII, 62830R (20 May 2006); doi: 10.1117/12.681852
Show Author Affiliations
Sachiko Kobayashi, Toshiba Corp. (Japan)
Suigen Kyoh, Toshiba Corp. (Japan)
Toshiya Kotani, Toshiba Corp. (Japan)
Satoshi Tanaka, Toshiba Corp. (Japan)
Soichi Inoue, Toshiba Corp. (Japan)


Published in SPIE Proceedings Vol. 6283:
Photomask and Next-Generation Lithography Mask Technology XIII
Morihisa Hoga, Editor(s)

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