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Proceedings Paper

Model based SRAF insertion check with OPC verify tools
Author(s): Chi-Yuan Hung; Zexi Deng; Gensheng Gao; Liguo Zhang; Qingwei Liu
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Paper Abstract

With the critical dimension of IC design decreases dramatically, to meet the yield target of the manufacture process, resolution enhancement technologies become extremely important nowadays. For 90nm technology node and below, sub rule assistant feature (SRAF) are usually employed to enhance the robustness of the micro lithography process. SRAF is really a powerful methodology to push the process limit for given equipment conditions. However, there is also a drawback of the SRAF. It is very hard to check the reasonability of the SRAF location, especially when SRAF is applied on full chips. This work is trying to demonstrate a model-based approach to do full-chip check of the SRAF insertion rule. First, we try to capture the lithography process information through real empirical wafer data. Then we try to check every SRAFs location and to find any hot spot that has the risk of being printed out on the wafer. Based on this approach, we can then not only apply full chip check to reduce the printability of SRAF. Furthermore, combined with DRC tools, we can find SRAFs that are inserted unreasonably and then apply modification on them.

Paper Details

Date Published: 20 May 2006
PDF: 6 pages
Proc. SPIE 6283, Photomask and Next-Generation Lithography Mask Technology XIII, 628332 (20 May 2006); doi: 10.1117/12.681820
Show Author Affiliations
Chi-Yuan Hung, Semiconductor Manufacturing International Corp. (China)
Zexi Deng, Semiconductor Manufacturing International Corp. (China)
Gensheng Gao, Mentor Graphics Corp. (China)
Liguo Zhang, Mentor Graphics Corp. (China)
Qingwei Liu, Semiconductor Manufacturing International Corp. (China)

Published in SPIE Proceedings Vol. 6283:
Photomask and Next-Generation Lithography Mask Technology XIII
Morihisa Hoga, Editor(s)

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