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Proceedings Paper

Lithography process margin enhancement using illumination based assist pattern
Author(s): James Moon; Dong-Jin Lee; Gui-Hwang Sim; Jae-Doo Eum; Byung-Ho Nam; Dong Gyu Yim
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Paper Abstract

The dawn of the Sub 100nm technology has brought many new exciting challenges for lithography process such as Immersion, OPC, asymmetry illumination, and so on. But, these new technology brought about new problems we face today due to shrinkage of the feature size. Some of the problems such as PR defect, ID bias and Mask Error Factor(MEF) are very important, but the most critical of all for lithography engineer is low process margin created by these technologies. In this study, we will be presenting the result of the Illumination based assist feature that enhances the lithography process margin for both Exposure Latitude (EL) and Depth Of Focus (DOF), while retaining safety of the scum generation by positioning the assist feature proportional to the illumination for 60nm device. Also, by automatically generating illumination based assist feature on the peripheral region of the mask, we will show that it levels the Critical Dimension (CD) uniformity for pattern of the same dimension located at both cell and peripheral region of the mask. Results will be tested on the mask feature size of 60nm and will be analyzed for both process margin and CD uniformity.

Paper Details

Date Published: 20 May 2006
PDF: 9 pages
Proc. SPIE 6283, Photomask and Next-Generation Lithography Mask Technology XIII, 62832X (20 May 2006); doi: 10.1117/12.681814
Show Author Affiliations
James Moon, Hynix Semiconductor Inc. (South Korea)
Dong-Jin Lee, Hynix Semiconductor Inc. (South Korea)
Gui-Hwang Sim, Hynix Semiconductor Inc. (South Korea)
Jae-Doo Eum, Hynix Semiconductor Inc. (South Korea)
Byung-Ho Nam, Hynix Semiconductor Inc. (South Korea)
Dong Gyu Yim, Hynix Semiconductor Inc. (South Korea)


Published in SPIE Proceedings Vol. 6283:
Photomask and Next-Generation Lithography Mask Technology XIII
Morihisa Hoga, Editor(s)

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