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Proceedings Paper

The design and qualification of the TEL CLEAN TRACK ACT M photomask coating tool at Intel
Author(s): Andrew Jamieson; Thuc Dam; Ki-Ho Baik; Ken Duerksen; Elie Eidson; Keiji Akai; Kazuya Hisano; Norifumi Kohama; Shinichi Machidori
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Paper Abstract

As photomask complexity has increased, mask manufacturing has become significantly more challenging. Tightening specs on defect performance, resolution, and CD control have pushed mask manufacturing to achieve levels that nearly match wafer capabilities. To meet wafer manufacturing needs, mask production requires high yield and quick turn-around time, resulting in an increased demand for very high equipment reliability. In-line resist coating capability is important to meet these demands; both for robust 2nd level phase-shift coating processes, and the enablement of advanced 1st-level process development with new resists and new resist process conditions. Intel Corporation worked with Tokyo Electron Ltd (TEL) to bring one of the first CLEAN TRACK ACT M (ACT M) units through design, acceptance tests and into manufacturing. TEL's CLEAN TRACK ACT M is a resist coating tool based on the CLEAN TRACK ACT12 (ACT 12) wafer manufacturing platform, and contains multiple mask-specific modules including advanced softbake oven units, edge-bead removal modules, and cleaning systems. After setup and optimization, the tool shows impressive performance, (for example, within-plate thickness uniformity of < 8A (3s) for certain processes). The motivation of the tool layout is discussed thoroughly. Elements of the module designs and their performance are shown. The acceptance testing performance is presented and includes: cleaning capabilities, oven performance, thickness performance, coating defect levels and edge bead removal capabilities. Finally, there is a limited discussion of manufacturing performance.

Paper Details

Date Published: 20 May 2006
PDF: 8 pages
Proc. SPIE 6283, Photomask and Next-Generation Lithography Mask Technology XIII, 62831P (20 May 2006); doi: 10.1117/12.681751
Show Author Affiliations
Andrew Jamieson, Intel Corp. (United States)
Thuc Dam, Intel Corp. (United States)
Ki-Ho Baik, Intel Corp. (United States)
Ken Duerksen, Tokyo Electron America (United States)
Elie Eidson, Tokyo Electron America (United States)
Keiji Akai, Tokyo Electron America (United States)
Kazuya Hisano, Tokyo Electron Kyushu Ltd. (Japan)
Norifumi Kohama, Tokyo Electron Kyushu Ltd. (Japan)
Shinichi Machidori, Tokyo Electron Kyushu Ltd. (Japan)

Published in SPIE Proceedings Vol. 6283:
Photomask and Next-Generation Lithography Mask Technology XIII
Morihisa Hoga, Editor(s)

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