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Proceedings Paper

Faster and smaller hardware implementation of XTR
Author(s): Michael Neve; Eric Peeters; Guerric Meurice de Dormale; Jean-Jacques Quisquater
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Paper Abstract

Modular multiplication is the core of most Public Key Cryptosystems and therefore its implementation plays a crucial role in the overall efficiency of asymmetric cryptosystems. Hardware approaches provide advantages over software in the framework of efficient dedicated accelerators. The concerns of the designers are mainly the die size, frequency, latency (throughput) and power consumption of those solutions. We show in this paper how Booth recoding, pipelining, Montgomery modular multiplication and carry save adders offer an attractive solution for hardware modular multiplication. Although most of the hereafter techniques stand as state-of-the-art, the combination described here is unique and particularly efficient in the context of constrained hardware design of XTR cryptosystem. Our solution is implemented on an FPGA platform and compared with previous results. The area-time ratio is improved by around a factor of 3.

Paper Details

Date Published: 25 August 2006
PDF: 12 pages
Proc. SPIE 6313, Advanced Signal Processing Algorithms, Architectures, and Implementations XVI, 631309 (25 August 2006); doi: 10.1117/12.680441
Show Author Affiliations
Michael Neve, UCL Crypto Group (Belgium)
Eric Peeters, UCL Crypto Group (Belgium)
Guerric Meurice de Dormale, UCL Crypto Group (Belgium)
Jean-Jacques Quisquater, UCL Crypto Group (Belgium)


Published in SPIE Proceedings Vol. 6313:
Advanced Signal Processing Algorithms, Architectures, and Implementations XVI
Franklin T. Luk, Editor(s)

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