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Proceedings Paper

Estimating adders for a low density parity check decoder
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Paper Abstract

Low density parity check decoders use computation nodes with multioperand adders on their critical path. This paper describes the design of estimating multioperand adders to reduce the latency, power and area of these nodes. The new estimating adders occasionally produce inaccurate results. The effect of these errors and the subsequent trade-off between latency and decoder frame error rate is examined. For the decoder investigated it is found that the estimating adders do not degrade the frame error rate.

Paper Details

Date Published: 25 August 2006
PDF: 9 pages
Proc. SPIE 6313, Advanced Signal Processing Algorithms, Architectures, and Implementations XVI, 631302 (25 August 2006); doi: 10.1117/12.680199
Show Author Affiliations
Braden J. Phillips, The Univ. of Adelaide (Australia)
Daniel R. Kelly, The Univ. of Adelaide (Australia)
Brian W. Ng, The Univ. of Adelaide (Australia)


Published in SPIE Proceedings Vol. 6313:
Advanced Signal Processing Algorithms, Architectures, and Implementations XVI
Franklin T. Luk, Editor(s)

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