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Proceedings Paper

System Verilog modelling of FIR filters
Author(s): Łukasz Pawlus; Marek Wegrzyn
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Paper Abstract

In the paper modelling of FIR filters by means of Verilog and SystemVerilog is presented. Hardware/software co-design approach for such systems is applied in the presented design. As a final technology for a FIR filters system implementation, a FPSLIC device is considered. Filters system demonstrates example methods of communication between FPGA and AVR microcontroller in a FPSLIC structure, i.e. the communication through SRAM memory, addressing lines, data bus, interrupts. It also demonstrates how to serve peripheral elements in FPSLIC device by means of DPI interface. FIR filters model contains also interface which implements a FPSLIC cache logic and gives opportunity to a dynamical reconfiguration of FPGA in a FPSLIC structure.

Paper Details

Date Published: 26 April 2006
PDF: 7 pages
Proc. SPIE 6159, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments IV, 61590G (26 April 2006); doi: 10.1117/12.674858
Show Author Affiliations
Łukasz Pawlus, Univ. of Zielona Gora (Poland)
Marek Wegrzyn, Univ. of Zielona Gora (Poland)


Published in SPIE Proceedings Vol. 6159:
Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments IV
Ryszard S. Romaniuk, Editor(s)

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