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Proceedings Paper

Characterization of across-device linewidth variation (ADLV) for 65-nm logic SRAM using CDSEM and linewidth roughness algorithms
Author(s): W. Chu; C. Radens; B. Dirahoui; I. Grauer; D. Samuels; S. Credendino; A. Nomura; R. Cornell
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Paper Abstract

The lithographic challenges of printing at low-k1 for 65 nm logic technologies have been well-documented (1,2). Heavy utilization of model-based optical proximity correction (OPC) and reticle enhancement technologies (RET) are the course of record for 65 nm logic nodes and below. Within the SRAM cells, often more dimensionally constrained than random logic, characterization of the nominal gate linewidth and linewidth variation is critical to ensure cell performance and stability. In this paper, we present the use of the linewidth roughness analysis package of a commercially-available CD SEM to extract low-spatial frequency information in order to characterize effects of OPC, substrate topography, process variations, and RETs. The SEM-based characterization of across-device linewidth variation is analyzed statistically to extract the information necessary to set device processing conditions and to make layout corrections consistent with producing the least possible channel length variation along the active device.

Paper Details

Date Published: 24 March 2006
PDF: 10 pages
Proc. SPIE 6152, Metrology, Inspection, and Process Control for Microlithography XX, 61520Y (24 March 2006); doi: 10.1117/12.663446
Show Author Affiliations
W. Chu, IBM Semiconductor Research and Development Ctr. (United States)
C. Radens, IBM Semiconductor Research and Development Ctr. (United States)
B. Dirahoui, IBM Semiconductor Research and Development Ctr. (United States)
I. Grauer, IBM Semiconductor Research and Development Ctr. (United States)
D. Samuels, IBM Semiconductor Research and Development Ctr. (United States)
S. Credendino, IBM Semiconductor Research and Development Ctr. (United States)
A. Nomura, AMD Corp. (United States)
R. Cornell, Applied Materials (United States)


Published in SPIE Proceedings Vol. 6152:
Metrology, Inspection, and Process Control for Microlithography XX
Chas N. Archie, Editor(s)

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