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Proceedings Paper

Modelling an optically interconnected FPGA for reconfigurable computing architectures
Author(s): G. A. Russell; C. J. Moir; J. F. Snowdon
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Paper Abstract

A series of electronic models, both analog and digital, have been developed to simulate the behaviour of a field programmable gate array chip with optoelectronics providing access to an optical interconnect fabric. The minimum latency of a 320Mbits-1 system was found to be 158.5ns.

Paper Details

Date Published: 21 April 2006
PDF: 8 pages
Proc. SPIE 6185, Micro-Optics, VCSELs, and Photonic Interconnects II: Fabrication, Packaging, and Integration, 61850I (21 April 2006); doi: 10.1117/12.662718
Show Author Affiliations
G. A. Russell, Heriot-Watt Univ. (United Kingdom)
C. J. Moir, Heriot-Watt Univ. (United Kingdom)
J. F. Snowdon, Heriot-Watt Univ. (United Kingdom)


Published in SPIE Proceedings Vol. 6185:
Micro-Optics, VCSELs, and Photonic Interconnects II: Fabrication, Packaging, and Integration
Hugo Thienpont; Mohammad R. Taghizadeh; Peter Van Daele; Jürgen Mohr, Editor(s)

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