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Proceedings Paper

Silicon IP reuse standards for design for manufacturability
Author(s): Juan Antonio Carballo; Savithri Sundareswaran
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Paper Abstract

Design for Manufacturability (DFM) has become a major semiconductor topic that spans various issues, including issues related to lithography hardware limitations, and issues related to variability. There is, however, an issue that crosses multiple DFM domains: the need to reuse designed Silicon IP blocks or "cores" across various manufacturing processes. Unfortunately, there are no standards to facilitate the reuse of circuit blocks while addressing the lithography- and variability-related issues. Specifically, there is no clear definition for a user of a core to evaluate "manufacturability" of a core for a set of foundry processes. We present a quantitative DFM standard for Silicon IP reuse, which addresses this problem. This work was done in conjunction with VSIA's DFM team.

Paper Details

Date Published: 14 March 2006
PDF: 11 pages
Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 615606 (14 March 2006); doi: 10.1117/12.659829
Show Author Affiliations
Juan Antonio Carballo, IBM Corp. (United States)
Savithri Sundareswaran, Freescale Semiconductor, Inc. (United States)

Published in SPIE Proceedings Vol. 6156:
Design and Process Integration for Microelectronic Manufacturing IV
Alfred K. K. Wong; Vivek K. Singh, Editor(s)

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