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Proceedings Paper

Automated CD-SEM recipe creation: a new paradigm in CD-SEM utilization
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Paper Abstract

As the trends in integrated circuit fabrication follow Moore's Law to smaller feature sizes, one trend seen in lithographic technology is the continually increasing use of optical enhancements such as Optical Proximity Correction (OPC). Small size perturbations are designed into the nominal feature shapes on the reticle such that the intended shape is printed. Verifying the success of OPC is critical to ramp-up and production of new process technologies. CD-SEMs are imaging tools which are capable of measuring feature sizes in any part of a chip, either in a test structure or within a circuit. A new trend in CD-SEM utilization is the implementation of automated recipe generation of complex CD-SEM recipes. The DesignGauge system uses design-to-SEM recipe creation and data collection. Once the recipe creation flow is implemented, the task of recipe creation can be accomplished within minutes. These applications enable a CD-SEM to be utilized to collect data for very complex OPC CD-SEM recipe runs which measure many different unique linewidths, spaces, and pattern placements within a circuit to check OPC success and lithographic fidelity. The data collection can provide accurate data results that can be utilized for comparing achieved feature measurements to nominal values from the design layout. This new application adds much value to the CD-SEM compared to other technologies such as OCD, as it completes the evaluation of in-circuit behavior to test structures in a scribe lane, something OCD currently cannot do. The present work evaluates the capabilities of DesignGauge, which is available for the latest-generation Hitachi S-9380II CD-SEMs. The evaluation includes rigorous tests of navigation, pattern recognition success rates, SEM image placement, throughput of recipe creation and recipe execution.

Paper Details

Date Published: 24 March 2006
PDF: 16 pages
Proc. SPIE 6152, Metrology, Inspection, and Process Control for Microlithography XX, 61521B (24 March 2006); doi: 10.1117/12.659759
Show Author Affiliations
Benjamin Bunday, International SEMATECH Manufacturing Initiative (United States)
William Lipscomb, International SEMATECH Manufacturing Initiative (United States)
John Allgair, International SEMATECH Manufacturing Initiative (United States)
Freescale Semiconductor, Inc. (United States)
Kyoungmo Yang, Hitachi High-Technologies Corp. (Japan)
Shunsuke Koshihara, Hitachi High-Technologies Corp. (Japan)
Hidetoshi Morokuma, Hitachi High-Technologies Corp. (Japan)
Lorena Page, Hitachi High Technologies America, Inc. (United States)
Alex Danilevsky, Hitachi High Technologies America, Inc. (United States)


Published in SPIE Proceedings Vol. 6152:
Metrology, Inspection, and Process Control for Microlithography XX
Chas N. Archie, Editor(s)

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