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Proceedings Paper

A novel approach to characterize trench depth and profile using the 3D tilt capability of a critical dimension-scanning electron microscope at 65nm technology mode
Author(s): R. Srivastava; P. Yelehanka; H. A. Kek; S. L. Ng; V. Srinivasan; R. Peltinov
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Paper Abstract

The use of dual-damascene (DD) technique for integration of Cu with low-k dielectric films has introduced new issues and challenges for the plasma etching processes. The two big challenges are: precise critical dimension (CD) control and good etch rate control over trench formation. Many details of the trench etch, such as Trench Depth, bottom rounding and sidewall smoothness have an effect on the device performance. One of the most important trench etch parameters is the trench depth. Proper control of the etch process to obtain the desired trench depth will directly impact the RC delay of the integrated circuit. There are several methods used in measuring trench depth and analyzing the trench profile. The most direct method will be to perform a cross-sectional analysis but this process is destructive. Other non-destructive conventional methods require physical contact with the wafer during measurement. For example: atomic force microscopy, high resolution profiler, etc. In this paper, we study the feasibility of using Applied Materials (AMAT) VeritySEM's 3D capabilities to characterize the trench depth and profiles without physically contacting the wafer. The main advantage of using a CDSEM tool to perform profile analysis is the productivity factor. This analysis can take place while also performing traditional CD measurement. This will eliminate the amount of queue time required on a conventional tool for profile measurement. As a result, an "in-situ" robust profile measurement recipe with good repeatability will improve the efficiency of the fab operations. In addition this approach is nondestructive and does not need any physical contact to the wafer.

Paper Details

Date Published: 24 March 2006
PDF: 6 pages
Proc. SPIE 6152, Metrology, Inspection, and Process Control for Microlithography XX, 61524I (24 March 2006); doi: 10.1117/12.659717
Show Author Affiliations
R. Srivastava, Chartered Semiconductor Manufacturing Ltd. (Singapore)
P. Yelehanka, Chartered Semiconductor Manufacturing Ltd. (Singapore)
H. A. Kek, Applied Materials South East Asia Pte. Ltd. (Singapore)
S. L. Ng, Applied Materials South East Asia Pte. Ltd. (Singapore)
V. Srinivasan, Applied Materials South East Asia Pte. Ltd. (Singapore)
R. Peltinov, Applied Materials Israel (Israel)

Published in SPIE Proceedings Vol. 6152:
Metrology, Inspection, and Process Control for Microlithography XX
Chas N. Archie, Editor(s)

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