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Proceedings Paper

Litho-metrology challenges for the 45-nm technology node and beyond
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Paper Abstract

There are numerous metrology challenges facing photolithography for the 45 nm technology node and beyond in the areas of critical dimension (CD), overlay and defect metrology. Many of these challenges are identified in the 2005 International Technology Roadmap for Semiconductors (ITRS) [1]. The Lithography and Metrology sections of the ITRS call for measurement of 45/32/22/18 nm generation linewidth and overlay. Each subsequent technology generation requires less variation in CD linewidth and overlay control, which results in a continuing need for improved metrology precision. In addition, there is an increasing need to understand individual edge variation and edge placement errors relative to the intended design. This is accelerating the need for new methods of CD and overlay measurement, as well as new target structures. This paper will provide a comprehensive overview of the CD and overlay metrology challenges for photolithography, taking into account the areas addressed in the 2005 ITRS for the 45 nm technology generation and beyond.

Paper Details

Date Published: 24 March 2006
PDF: 15 pages
Proc. SPIE 6152, Metrology, Inspection, and Process Control for Microlithography XX, 61520C (24 March 2006); doi: 10.1117/12.659059
Show Author Affiliations
John A. Allgair, International SEMATECH Manufacturing Initiative (United States)
Freescale Semiconductor (United States)
Benjamin D. Bunday, International SEMATECH Manufacturing Initiative (United States)
Mike Bishop, International SEMATECH Manufacturing Initiative (United States)
Pete Lipscomb, International SEMATECH Manufacturing Initiative (United States)
Ndubuisi G. Orji, National Institute of Standards and Technology (United States)


Published in SPIE Proceedings Vol. 6152:
Metrology, Inspection, and Process Control for Microlithography XX
Chas N. Archie, Editor(s)

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