Share Email Print
cover

Proceedings Paper

Reticle enhancement verification for the 65nm and 45nm nodes
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

In the last 2 years, the semiconductor industry has recognized the critical importance of verification for optical proximity correction (OPC) and reticle/resolution enhancement technology (RET). Consequently, RET verification usage has increased and improved dramatically. These changes are due to the arrival of new verification tools, new companies, new requirements and new awareness by product groups about the necessity of RET verification. Currently, as the 65nm device generation comes into full production and the 45nm generation starts full development, companies now have the tools and experience (i.e., long lists of previous errors to avoid) needed to perform a detailed analysis of what is required for 45nm and 65nm RET verification. In previous work [1] we performed a theoretical analysis of OPC & RET verification requirements for the 65nm and 45nm device generations and drew conclusions for the ideal verification strategy. In this paper, we extend the previous work to include actual observed verification issues and experimental results. We analyze the historical experimental issues with regard to cause, impact and optimum verification detection strategy. The results of this experimental analysis are compared to the theoretical results, with differences and agreement noted. Finally, we use theoretical and experimental results to propose an optimized RET verification strategy to meet the user requirements of 45nm development and the differing requirements of 65nm volume production.

Paper Details

Date Published: 14 March 2006
PDF: 12 pages
Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 61560R (14 March 2006); doi: 10.1117/12.658823
Show Author Affiliations
Kevin Lucas, Freescale Semiconductor (France)
Kyle Patterson, Freescale Semiconductor (France)
Robert Boone, Freescale Semiconductor (France)
Corinne Miramond, STMicroelectronics (France)
Amandine Borjon, Philips Semiconductor (France)
Jerome Belledent, Philips Semiconductor (France)
Olivier Toublan, Mentor Graphics Europe (France)
Jorge Entradas, Mentor Graphics Europe (France)
Yorick Trouiller, LETI/CEA (France)


Published in SPIE Proceedings Vol. 6156:
Design and Process Integration for Microelectronic Manufacturing IV
Alfred K. K. Wong; Vivek K. Singh, Editor(s)

© SPIE. Terms of Use
Back to Top