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Proceedings Paper

Modeling edge placement error distribution in standard cell library
Author(s): Puneet Gupta; Andrew B. Kahng; Swamy V. Muddu; Sam Nakagawa
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Paper Abstract

In this work we present a predictive model for the edge placement error (EPE) distribution of devices in standard library cells based on lithography simulations of selective test patterns. Poly-silicon linewidth variation in the sub-100nm technology nodes is a major source of transistor performance variation (e.g., Ion and Ioff) and circuit parametric yield. It has been reported that significant part of the observed variation is systematically impacted by the neighboring layout pattern within optical proximity. Design optimization should account for this variation in order to maximize the performance and manufacturability of chip designs. We focus our analysis on standard library cells. In the past the EPE characterization was done on simple line array structures. However, the real circuit contexts are much more complex. Standard library cells offer a nice balance of usability by the designers and modeling complexity. We first construct a set of canonical test structures to perform lithography simulations using various OPC parameters and under various focus and exposure conditions. We then analyze the simulated printed image and capture the layout-dependent characteristics of the EPE distribution. Subsequently, our model estimates the EPE distribution of library cells based on their layout. In contrast to a straight-forward simulation of the library cells themselves, this approach is computationally less expensive. In addition the model can be used to predict the EPE distribution of any library cells and not limited to those that are simulated. Also, since the model encapsulates the details of lithography, it is easier for designers to integrate into design flow.

Paper Details

Date Published: 14 March 2006
PDF: 12 pages
Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 61560S (14 March 2006); doi: 10.1117/12.658580
Show Author Affiliations
Puneet Gupta, Blaze DFM, Inc. (United States)
Andrew B. Kahng, Blaze DFM, Inc. (United States)
Swamy V. Muddu, Univ. of California, San Diego (United States)
Sam Nakagawa, Blaze DFM, Inc. (United States)


Published in SPIE Proceedings Vol. 6156:
Design and Process Integration for Microelectronic Manufacturing IV
Alfred K. K. Wong; Vivek K. Singh, Editor(s)

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