Share Email Print
cover

Proceedings Paper

Lithography simulation-based full-chip design analyses
Author(s): Puneet Gupta; Andrew B. Kahng; Sam Nakagawa; Saumil Shah; Puneet Sharma
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

Today's design flows sign-off performance and power prior to application of resolution enhancement techniques (RETs). Together with process variations, RETs can lead to substantial difference between post-layout and on-silicon performance and power. Lithography simulation enables estimation of on-silicon feature sizes at different process conditions. However, current lithography simulation tools are completely shape-based and not connected to the design in any way. This prevents designers from estimating on-silicon performance and power and consequently most chips are designed for pessimistic worst-cases. In this paper we present a novel methodology that uses the result of lithography simulation for estimation of performance and power of a design using standard device- and chip-level analysis tools. The key challenge addressed by our methodology is to transform shapes generated by lithography simulation to a form that is acceptable by standard analysis tools such that electrical properties are preserved. Our approach is sufficiently fast to be run full-chip on all layers of a large design. We observe that while the difference in power and performance estimates at post-layout and on-silicon is small at ideal process conditions, it increases substantially at non-ideal process conditions. With our RET recipes, linewidths tend to decrease with defocus for most patterns. According to the proposed analyses of layouts litho-simulated at 100nm defocus, leakage increases by up to 68%, setup time improves by up to 14%, and dynamic power reduces by up to 2%. The key challenge addressed by our methodology is to transform shapes generated by lithography simulation to a form that is acceptable by standard analysis tools such that electrical properties are preserved. Our approach is sufficiently fast to be run full-chip on all layers of a large design. We observe that while the difference in power and performance estimates at post-layout and on-silicon is small at ideal process conditions, it increases substantially at non-ideal process conditions. With our RET recipes, linewidths tend to decrease with defocus for most patterns. According to the proposed analyses of layouts litho-simulated at 100nm defocus, leakage increases by up to 68%, setup time improves by up to 14%, and dynamic power reduces by up to 2%.

Paper Details

Date Published: 14 March 2006
PDF: 8 pages
Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 61560T (14 March 2006); doi: 10.1117/12.658129
Show Author Affiliations
Puneet Gupta, Blaze DFM Inc. (United States)
Andrew B. Kahng, Blaze DFM Inc. (United States)
Sam Nakagawa, Blaze DFM Inc. (United States)
Saumil Shah, Univ. of Michigan, Ann Arbor (United States)
Puneet Sharma, Univ. of California, San Diego (United States)


Published in SPIE Proceedings Vol. 6156:
Design and Process Integration for Microelectronic Manufacturing IV
Alfred K. K. Wong; Vivek K. Singh, Editor(s)

© SPIE. Terms of Use
Back to Top