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Proceedings Paper

Assessment of electron projection lithography mask membrane image placement accuracy due to fabrication processes
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Paper Abstract

Electron Projection Lithography (EPL) has been identified as a viable candidate of the next-generation lithography technologies for the sub-65-nm nodes. The development of a low-distortion mask is essential for meeting the stringent requirements at these lower nodes. This research focused on predicting the influence of mask fabrication and pattern transfer on the image placement (IP) accuracy of a 200-mm EPL mask. In order to quantify the in-plane distortions of the freestanding membranes, three-dimensional finite element (FE) models (full mask and submodels) have been developed. A typical process flow including thin-film deposition, pattern transfer, and tool chucking was simulated with the FE models. Full mask models were used to characterize the global response of the mask, whereas submodels of the individual membranes provided details of the localized distortions on a subfield-by-subfield basis. In addition, local (subfield) correction schemes were replicated in the FE simulations. A parametric study was conducted to identify critical variables in the mask fabrication process. Pattern transfer was modeled using appropriate equivalent modeling techniques. IP errors of membranes with patterned areas of 4 mm × 4 mm and 1 mm × 1 mm were compared in the current study, illustrating the advantages / disadvantages of the two formats. The numerical models developed here have been used to investigate the proposed EPL mask formats, as well as the materials, fabrication processes, and general system parameters required to achieve the necessary pattern placement accuracy.

Paper Details

Date Published: 23 March 2006
PDF: 10 pages
Proc. SPIE 6151, Emerging Lithographic Technologies X, 61511J (23 March 2006); doi: 10.1117/12.657659
Show Author Affiliations
Michael J. Boruszewski, Univ. of Wisconsin-Madison (United States)
Roxann L. Engelstad, Univ. of Wisconsin-Madison (United States)
Gerald A. Dicks, Univ. of Wisconsin-Madison (United States)
Hiroshi Sakaue, Semiconductor Leading Edge Technologies, Inc. (Japan)
Hiroshi Arimoto, Semiconductor Leading Edge Technologies, Inc. (Japan)


Published in SPIE Proceedings Vol. 6151:
Emerging Lithographic Technologies X
Michael J. Lercel, Editor(s)

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