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Proceedings Paper

Reducing DfM to practice: the lithography manufacturability assessor
Author(s): Lars Liebmann; Scott Mansfield; Geng Han; James Culp; Jason Hibbeler; Roger Tsai
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Paper Abstract

The need for accurate quantification of all aspects of design for manufacturability using a mutually compatible set of quality-metrics and units-of-measure, is reiterated and experimentally verified. A methodology to quantify the lithography component of manufacturability is proposed and its feasibility demonstrated. Three stages of lithography manufacturability assessment are described: process window analysis on realistic integrated circuits following layout manipulations for resolution enhancement and the application of optical proximity correction, failure sensitivity analysis on simulated achievable dimensional bounds (a.k.a. variability bands), and yield risk analysis on iso-probability bands. The importance and feasibility of this technique is demonstrated by quantifying the lithography manufacturability impact of redundant contact insertion and Critical Area optimization in units that can be used to drive an overall layout optimization. The need for extensive experimental calibration and improved simulation accuracy is also highlighted.

Paper Details

Date Published: 13 March 2006
PDF: 12 pages
Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 61560K (13 March 2006); doi: 10.1117/12.657139
Show Author Affiliations
Lars Liebmann, IBM Corp. (United States)
Scott Mansfield, IBM Corp. (United States)
Geng Han, IBM Corp. (United States)
James Culp, IBM Corp. (United States)
Jason Hibbeler, IBM Corp. (United States)
Roger Tsai, IBM Corp. (United States)


Published in SPIE Proceedings Vol. 6156:
Design and Process Integration for Microelectronic Manufacturing IV
Alfred K. K. Wong; Vivek K. Singh, Editor(s)

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