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Proceedings Paper

From poly line to transistor: building BSIM models for non-rectangular transistors
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Paper Abstract

Non-rectangular transistors in today's advanced processes pose a potential problem between manufacturing and design as today's compact transistor models have only one length and one width parameter to describe the gate dimensions. The transistor model is the critical link between manufacturing and design and needs to account for across gate CD variation as corner rounding along with other 2D proximity effects become more pronounced. This is a complex problem as threshold voltage and leakage current have a very complex non-linear relationship with gate length. There have been efforts trying to model non-rectangular gates as transistors in parallel, but this approach suffers from the lack of accurate models for "slice transistors", which could potentially necessitate new circuit simulators with new sets of complex equations. This paper will propose a new approach that approximates a non-rectangular transistor with an equivalent rectangular transistor and hence does not require a new transistor model or significant changes to circuit simulators. Effective length extraction consists of breaking a non-rectangular transistor into rectangular slices and then taking a weighted average based on simulated slice currents in HSPICE. As long as a different effective length is used for delay and static power analysis, simulation results show that the equivalent rectangular transistor behaves the same as a non-rectangular transistor.

Paper Details

Date Published: 13 March 2006
PDF: 9 pages
Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 61560P (13 March 2006); doi: 10.1117/12.657051
Show Author Affiliations
Wojtek J. Poppe, Univ. of California, Berkeley (United States)
Luigi Capodieci, AMD, pl. (United States)
Joanne Wu, AMD, pl. (United States)
Andrew Neureuther, Univ. of California, Berkeley (United States)


Published in SPIE Proceedings Vol. 6156:
Design and Process Integration for Microelectronic Manufacturing IV
Alfred K. K. Wong; Vivek K. Singh, Editor(s)

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