Share Email Print
cover

Proceedings Paper

Highly accurate hybrid-OPC method for sub-60nm memory device
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

Recently, as the design rule shrinks so does the CD tolerance. Therefore, the importance of simulation and OPC accuracy is increasing. In the past, when pattern size was large, rule-based OPC was acceptable but as the design rule shrinks accuracy of OPC turned to model-based OPC and almost all device uses this method. Model-based OPC is based on parameter fitting it has Model-Residual-Error (MRE). Due to this error the accuracy of the model has limitations. Usually variable-threshold or vector model is applied to the model in order to cut down the MRE. But still, size of the MRE is too large compared to CD tolerance. Currently, further development of model-based OPC resulted in creation of both model and rule-based OPC. This is called Hybrid OPC method. Hybrid-OPC method is based on model OPC but MRE can be lowered using rule bias to retarget the design data. But this method makes it difficult to retarget the design data in that rule biasing result is hard to predict after the model-based OPC operation. In this paper, we propose New Hybrid OPC method that feeds back the MRE calibrated data set to model-based OPC method. By using this method, better OPC model can be made. We will be presenting the result after the method has been applied on sub-60nm device and the capability of this method.

Paper Details

Date Published: 14 March 2006
PDF: 8 pages
Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 61561A (14 March 2006); doi: 10.1117/12.656853
Show Author Affiliations
Hyoung-Soon Yune, Hynix Semiconductor Inc. (South Korea)
Cheol-Kyun Kim, Hynix Semiconductor Inc. (South Korea)
Yeong-Bae Ahn, Hynix Semiconductor Inc. (South Korea)
Byung-Ho Nam, Hynix Semiconductor Inc. (South Korea)
Donggyu Yim, Hynix Semiconductor Inc. (South Korea)


Published in SPIE Proceedings Vol. 6156:
Design and Process Integration for Microelectronic Manufacturing IV
Alfred K. K. Wong; Vivek K. Singh, Editor(s)

© SPIE. Terms of Use
Back to Top