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Proceedings Paper

Process window OPC for reduced process variability and enhanced yield
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Paper Abstract

As the industry moves toward 45nm technology node and beyond, further reduction of lithographic process window is anticipated. The consequence of this is twofold: first, the manufactured chip will have pattern sizes that are different from the designed pattern sizes and those variations may become more dominated by systematic components as the process windows shrink; second, smaller process windows will lead to yield loss as, at small dimensions, lithographic process windows are often constrained by catastrophic fails such as resist collapse or trench scumming, rather than by gradual pattern size variation. With this notion, Optical Proximity Correction (OPC) for future technology generations must evolve from the current single process point OPC to algorithms that provide an OPC solution optimized for process variability and yield. In this paper, a Process Window OPC (PWOPC) concept is discussed, along with its place in the design-to-manufacturing flow. Use of additional models for process corners, integration of process fails and algorithm optimization for a production-worthy flow are described. Results are presented for 65nm metal levels.

Paper Details

Date Published: 20 March 2006
PDF: 12 pages
Proc. SPIE 6154, Optical Microlithography XIX, 61543L (20 March 2006); doi: 10.1117/12.656835
Show Author Affiliations
Azalia Krasnoperova, IBM Systems and Technology Group (United States)
James A. Culp, IBM Systems and Technology Group (United States)
Ioana Graur, IBM Systems and Technology Group (United States)
Scott Mansfield, IBM Systems and Technology Group (United States)
Mohamed Al-Imam, Mentor Graphics Corp. (Egypt)
Hesham Maaty, Mentor Graphics Corp. (Egypt)


Published in SPIE Proceedings Vol. 6154:
Optical Microlithography XIX
Donis G. Flagello, Editor(s)

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