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Proceedings Paper

RET for the wiring layer of a 3D memory
Author(s): Yung-Tin Chen; Paul Poon; Chris Petti; Vishnu Kamat; Apo Sezginer; Hsu-Ting Huang
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Paper Abstract

A typical wiring layer of SanDisk 3-dimensional memory device includes a dense array of lines. Every other line terminates in an enlarged contact pad at the edge of the array. The pitch of the pads is twice the pitch of the dense array. When process conditions are optimized for the dense array, the gap between the pads becomes a weak point. The gap has a smaller depth of focus. As defocus increases, the space between the pads diminishes and bridges. We present a method of significantly increasing the depth of focus of the pads at the end of the dense array. By placing sub-resolution cutouts in the pads, we equalize the dominant pitch of the pads and the dense array.

Paper Details

Date Published: 14 March 2006
PDF: 8 pages
Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 61561E (14 March 2006); doi: 10.1117/12.656725
Show Author Affiliations
Yung-Tin Chen, SanDisk, Inc. (United States)
Paul Poon, SanDisk, Inc. (United States)
Chris Petti, SanDisk, Inc. (United States)
Vishnu Kamat, Invarium Inc. (United States)
Apo Sezginer, Invarium Inc. (United States)
Hsu-Ting Huang, Invarium Inc. (United States)


Published in SPIE Proceedings Vol. 6156:
Design and Process Integration for Microelectronic Manufacturing IV
Alfred K. K. Wong; Vivek K. Singh, Editor(s)

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