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Proceedings Paper

Illumination conditions matching for critical layers manufacturing in a production context
Author(s): Louis-Pierre Armellin; Andreas Torsy; Ken Hernan; Gurwan Kerrien; Johanna Guidet; Yan Riopel; Vincent Salvetat
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Paper Abstract

As device geometries shrink, the lithography solutions to satisfy production requirements for a manufacturable process window often includes Optical Proximity Correction (OPC). OPC is sensitive to many process parameters, one of the most important is the illumination condition, this implicitly includes the lens NA and illuminator NA that generate the partial coherence factor σ, of the scanner. In a production context, the same performance is required for the product using several exposure tools but only one OPC scheme; this requires that the illumination conditions between scanners are matched. This verification has to be done not only for tools of the same generation, but the more complex case between tools of different generations. For the gate layer, an important requirement is the Across Chip Linewidth Variation (ACLV) that ensures transistors performance whatever the pitch. This requirement is mainly driven by Nested-Iso Bias. The paper will present the work completed on the gate layer in order to match the illumination conditions between scanners of the same generation and also between two scanners of different generations: one offers 0.68NA and a maximum σ of 0.75, the other has a maximum NA of 0.82 and maximum σ of 0.9. For scanners of the same generation, the matching was done by simply measuring the illumination NA of the tools, and for this a pinhole test was used. The matching was verified after litho by measuring Nested-Iso bias, and then on product using electrical CD measurement. For the "generation matching", two parameters are needed to define the illumination conditions: lens NA and illuminator NA. In this case, Nested-Iso bias is insufficient to identify the matching conditions as several combinations of lens and illuminator NA lead to the same Nested-Iso bias. Instead the OPC was checked on proximity curves generated for line end shortening and SRAM cells. The best matching conditions were then optimised using a simulation tool with the final check completed on product using electrical CD measurement.

Paper Details

Date Published: 20 March 2006
PDF: 9 pages
Proc. SPIE 6154, Optical Microlithography XIX, 61543V (20 March 2006); doi: 10.1117/12.656538
Show Author Affiliations
Louis-Pierre Armellin, Altis Semiconductor (France)
Andreas Torsy, Altis Semiconductor (France)
Ken Hernan, Altis Semiconductor (France)
Gurwan Kerrien, Altis Semiconductor (France)
Johanna Guidet, Altis Semiconductor (France)
Yan Riopel, Altis Semiconductor (France)
Vincent Salvetat, Nikon Precision Europe GmbH (France)


Published in SPIE Proceedings Vol. 6154:
Optical Microlithography XIX
Donis G. Flagello, Editor(s)

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