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Proceedings Paper

Experimental verification of improved printability for litho-driven designs
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Paper Abstract

The continued downscaling of the feature sizes and pitches for each new process generation increases the challenges for obtaining sufficient process control. As the dimensions approach the limits of the lithographic capabilities, new solutions for improving the printability are required. Including the design into the optimization process significantly improves the printability. The use of litho-driven designs becomes increasingly important towards the 45 nm node. The litho-driven design is applied to the active, gate, contact and metal layers. It has been shown previously, that the impact on the chip area is negligible. Simulations have indicated a significant improvement in controlling the critical dimensions of the gate layer. In this paper, we present our first results of an experimental validation of litho-driven designs printed on an immersion scanner. In our design we use a fixed pitch approach that allows to match the illumination conditions to those for the memory structures. The impact on the chip area and on the CD control will be discussed. The resulting improvement in CD control is demonstrated experimentally by comparing the experimental results of litho-driven and standard designs. A comparison with simulations will be presented.

Paper Details

Date Published: 14 March 2006
PDF: 11 pages
Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 61560O (14 March 2006); doi: 10.1117/12.656359
Show Author Affiliations
Johannes van Wingerden, Philips Research Europe (Belgium)
Laurent Le Cam, Philips Semiconductors (France)
Rene Wientjes, Philips Semiconductors CTO (Netherlands)
Michael Benndorf, Philips Research Europe (Belgium)
Yorick Trouiller, CEA-LETI (France)
Jerome Belledent, Philips Semiconductors (France)
Rob Morton, Philips Semiconductors (France)
Yuri Aksenov, Philips Research Europe (Belgium)


Published in SPIE Proceedings Vol. 6156:
Design and Process Integration for Microelectronic Manufacturing IV
Alfred K. K. Wong; Vivek K. Singh, Editor(s)

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