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Proceedings Paper

From speculation to specification: a discussion on how to define the tolerance of LER/LWR and its measurement methodology
Author(s): Atsuko Yamaguchi; Robert Steffen; Hiroki Kawada; Takashi Iizumi; Aritoshi Sugimoto
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Paper Abstract

Metrological definition and the target value of linewidth roughness (LWR) in gate pattern of MOSFETS are discussed. The effects of sampling interval of gate-LWR measurements using critical dimension scanning electron microscopy (CD-SEM) on the measurement accuracy was examined by both experiment and simulation. It was found that a 10-nm interval is sufficiently small to fully characterize roughness in a typically chosen 2-μm-long line with considering the LWR measurement error. Random image noise and intrinsic LWR variations are found to cause larger impacts on the measured value than the finiteness of the sampling interval. A practical procedure for improving the measurement accuracy is also discussed. Moreover, a methodology for establishing the gate-LWR target is proposed. Threshold-voltage shift caused by gate-LWR is given by using the LWR spectrum and the I-V curves of a transistor without LWR (ideal I-V curves). In order to calculate the target value, the ideal I-V curves, the typical gate width of the transistor and the tolerance for LWR-caused threshold-voltage variation are to be clarified.

Paper Details

Date Published: 24 March 2006
PDF: 8 pages
Proc. SPIE 6152, Metrology, Inspection, and Process Control for Microlithography XX, 61524O (24 March 2006); doi: 10.1117/12.656055
Show Author Affiliations
Atsuko Yamaguchi, Hitachi, Ltd. (Japan)
Robert Steffen, Hitachi High-Technologies Corp. (Japan)
Hiroki Kawada, Hitachi High-Technologies Corp. (Japan)
Takashi Iizumi, Hitachi High-Technologies Corp. (Japan)
Aritoshi Sugimoto, Hitachi High-Technologies Corp. (Japan)

Published in SPIE Proceedings Vol. 6152:
Metrology, Inspection, and Process Control for Microlithography XX
Chas N. Archie, Editor(s)

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