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Proceedings Paper

Energy-efficient error-control schemes for on-chip networks
Author(s): Min Zhang; Fengguang Luo; Yonghua Feng; Jia Hu
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Paper Abstract

On-chip networks (NoCs) for future Systems-on-chips (SoCs) will be required to consume as little energy as possible while satisfying other performance constraints. Meanwhile, NoCs has to deal with the increasing sensitivity of communication links to noise sources such as crosstalk or power supply noise. We focus on the communication reliability for NoCs from an energy-efficient viewpoint. Firstly, a new framework to implement error-control schemes is proposed. No encoders are needed for the communication switches of NoCs in this framework. Secondly, we model on-chip interconnect as noisy channels and evaluate the energy-efficiency of parallel error-detection codes through the experiments on two kinds of codes: PARITY code and Hamming code. The supply voltages Vdd are analyzed to meet the predefined reliability requirements. The results show that up to 15.4% power reduction can be achieved by parallel codes and it can make an appropriate trade-off between power, delay and wires.

Paper Details

Date Published: 5 January 2006
PDF: 5 pages
Proc. SPIE 5985, International Conference on Space Information Technology, 59850W (5 January 2006); doi: 10.1117/12.655827
Show Author Affiliations
Min Zhang, Huazhong Univ. of Science and Technology (China)
Fengguang Luo, Huazhong Univ. of Science and Technology (China)
Yonghua Feng, Huazhong Univ. of Science and Technology (China)
Jia Hu, Huazhong Univ. of Science and Technology (China)


Published in SPIE Proceedings Vol. 5985:
International Conference on Space Information Technology
Cheng Wang; Shan Zhong; Xiulin Hu, Editor(s)

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