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Proceedings Paper

A systematic study of missing via mechanism and its solutions
Author(s): Lei Wang; Wei Huang; Qiang Wu
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Paper Abstract

Missing via has been a very annoying defect in semiconductor manufacture especially to foundry. Its solution can be rather attractive in yield improvement for relatively mature technology since each percentage point improvement will mean significant profit margin enhancement. However, the root cause for the missing via defect is not easy find since many factors, such as, defocus, material re-deposition, and inadequate developing can lead to missing via defects. Therefore, being able to know the exact cause for each defect type is the key to the solution of the problem. In this paper, we will present the analysis methodology used in our company. In the experiments, we have observed three types of missing vias. The first type consists of large areas, usually circular, of missing patterns, which are primarily located near wafer edge. The second type consists of isolated sites with single partially opened vias or completely unopened vias. The third type consists of relatively small circular areas, within which the entire via pattern is missing. We have first tried the optimization of the developing recipe and found that the first type missing via can be largely removed through the tuning of the rinse process, which improves the cleaning efficiency of the developing residue. However, this method does not remove the missing via of the second type, or the third type. For the second type missing via, we have found that it is related to local defocus caused by topographical distribution. To resolve the third type missing via defects, we have performed extensive experiments with different types of developer nozzles and different types of photomasks and the result is that we have not found any distinct dependence of the defect density to either the nozzle and mask types. Besides, we have also studied the defect density from three resists with different resolution capability and we found a correlation between the defect density and the resist resolution. It seems that, in general, lower resolution resist also has lower defect density and the results will be presented in the paper.

Paper Details

Date Published: 24 March 2006
PDF: 5 pages
Proc. SPIE 6152, Metrology, Inspection, and Process Control for Microlithography XX, 61520A (24 March 2006); doi: 10.1117/12.655471
Show Author Affiliations
Lei Wang, Shanghai Huahong NEC Electronics Co., Ltd. (China)
Wei Huang, Shanghai Huahong NEC Electronics Co., Ltd. (China)
Qiang Wu, Shanghai Huahong NEC Electronics Co., Ltd. (China)


Published in SPIE Proceedings Vol. 6152:
Metrology, Inspection, and Process Control for Microlithography XX
Chas N. Archie, Editor(s)

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