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Proceedings Paper

Optimization of dual BARC structures for hyper-NA immersion lithography
Author(s): Nobuyuki N. Matsuzawa; Boontarika Thunnakart; Ken Ozawa; Yuko Yamaguchi; Hiroyuki Nakano; Hiroichi Kawahira
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Paper Abstract

For the purpose of finding feasible dual-BARC (Bottom Anti-Reflective Coating) parameters for immersion lithography that do not depend on the polarization of light, illumination conditions and pattern sizes and pitches, comprehensive optimizations of the dual-BARC parameters were performed. A computational code was developed that performs automatic and comprehensive optimizations of dual-BARC parameters under any kind of conditions. Margins of dual-BARC parameters, which assure the substrate reflectance to be lower than a desired value, were also estimated by using the code. Dual-BARC parameters to minimize the substrate reflectance were successfully obtained for the BARC formed on a silicon oxide and nitride layer for cases of NA being 1.0, 1.1, 1.2 and 1.3 to 1.4. The thickness of the silicon oxide and nitride layer was varied from 10 to 200 nm. It was found that the dual-BARC concept works up to NA = 1.1 and 1.4 for the BARC on a silicon oxide and a silicon nitride layer, respectively, although for the case of the dual BARC on a silicon oxide layer, the range of the thickness of the oxide layer where the dual-BARC concept works is limited. In addition, for both of the cases of the dual BARC on silicon oxide and nitride, it was calculated that the top-layer of the dual BARC has to be extremely thin. Feasibility of using a layer structure consisting of a planarization and hardmask layer as a reflection-control structure was also examined. This showed that this concept can work up to NA = 1.2 and 1.4 for the case on silicon oxide and nitride, respectively. Finally, a routine to optimize graded-BARC structure was successfully implemented into our computational code. By using the routine, advantages of the graded-BARC concept over the dual-BARC concept in terms of suppressing substrate reflectance were demonstrated.

Paper Details

Date Published: 29 March 2006
PDF: 12 pages
Proc. SPIE 6153, Advances in Resist Technology and Processing XXIII, 61531J (29 March 2006); doi: 10.1117/12.651563
Show Author Affiliations
Nobuyuki N. Matsuzawa, Sony Corp. (Japan)
Boontarika Thunnakart, Sony Corp. (Japan)
Ken Ozawa, Sony Corp. (Japan)
Yuko Yamaguchi, Sony Corp. (Japan)
Hiroyuki Nakano, Sony Corp. (Japan)
Hiroichi Kawahira, Sony Corp. (Japan)

Published in SPIE Proceedings Vol. 6153:
Advances in Resist Technology and Processing XXIII
Qinghuang Lin, Editor(s)

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