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Proceedings Paper

Wafer bonding for 3D integration of MEMS/CMOS
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Paper Abstract

The pressure for reduction in cost and development time in new product, together with the need to pack more functions into smaller volumes in silicon chips has been fueling the system-on-chip (SOC) development. However, the current SOC technologies available essentially involve merging of chips fabricated with standard CMOS technology. These SOC technologies provide an integration solution with compatible fabrication processes that require little changes in process integration. There is no standard cost-effective solution to make 3D MEMS and optoelectronic devices together with CMOS on the same chip without compromising material compatibility, process complexity and system performance. One solution is to fabricate MEMS and CMOS components on separate wafer substrates and then stack them together with well isolated interconnected vias. In order to demonstrate this wafer-level 3D integration technology, a novel wafer-level bonding technology is being developed. This paper reports a detailed study of 3D MEMS (Micro Electro-Mechanical Systems) integration through multi-wafer anodic and polymeric wafer bonding. Different from previously reported wafer bonding studies, this study focuses on the optimization of the bonding process to improve the bonding quality.

Paper Details

Date Published: 5 January 2006
PDF: 8 pages
Proc. SPIE 6111, Reliability, Packaging, Testing, and Characterization of MEMS/MOEMS V, 61110O (5 January 2006); doi: 10.1117/12.646467
Show Author Affiliations
Alison Gracias, Univ. at Albany/SUNY (United States)
James Castracane, Univ. at Albany/SUNY (United States)
Bai Xu, Univ. at Albany/SUNY (United States)

Published in SPIE Proceedings Vol. 6111:
Reliability, Packaging, Testing, and Characterization of MEMS/MOEMS V
Danelle M. Tanner; Rajeshuni Ramesham, Editor(s)

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